Date:  July 28, 2014
Time:  9:00 a.m. – 3:30 p.m.
Location:  5628 Math Science, Visualization Portal

RSVP is required: Please RSVP online

Note: If you have a challenge compute problem, and you can outline where your program spends most time, we want to hear from you at this meeting. Please contact us at hpc@ucla.edu to participate.

ManyCore Computing: Harnessing the Power of Next Generation Architectures for Compute Intensive Applications:

Existing and emerging applications ranging from scientific computing, to big data, to context-aware computing will continue to drive microprocessor designers to improve performance to new heights.  While performance is crucial for these applications, power-efficiency has become a primary microprocessor design goal in the many-core era.  Therefore, current and future generation microprocessors have abandoned frequency scaling, and instead leverage parallelism, heterogeneity, reconfigurability, and domain-specific enhancement to provide power-efficient performance.

The overwhelming majority of microprocessor designs these days leverage parallelism in some way, whether it be the thread-level parallelism seen in many-core and/or hyperthreaded designs or the instruction-level parallelism exploited in dynamically scheduled processors.  Heterogeneous designs feature different types of cores and other on-chip components that enable application writers to map their software to the appropriate hardware for optimal power efficiency.  For example, complex out-of-order cores can be used for sequential code while larger pools of simple in-order cores can be used for parallel portions of the code.  Reconfigurability enables an architecture to adapt to the specific needs of different applications or different data inputs – and may be implemented in a variety of granularities, from voltage or frequency scaling to fully programmable fabric (i.e. FPGAs).  Domain-specific enhancement means that architectures provide features that are specialized for particular classes of applications – such as ASIC accelerators designed to provide power efficient implementation of encryption/decryption. Domain-specific designs (whether they be implemented in ASIC or FPGA) can provide orders of magnitude improvement in power-efficiency over general purpose processors, but they lack reusability across different application domains, and significantly increase the overall design time and cost.

Therefore, while emerging microprocessor technologies offer potential speedups, their inherent complexity make it challenging for application writers and domain experts. Compilers and translators cannot map existing code to newer microprocessor designs without the domain experts first adapting their software to a new set of demands and limitations.

The mandate of this new IDRE focus group is to bring together experts in microprocessor design, software systems, and application domains to exchange ideas on these emerging trends.  Microprocessor designers and system software builders will benefit from better understanding the issues faced by application designers, particularly for domain-specific designs. Application designers will usually design for current generation hardware, but microprocessor designers and system software builders need a better picture of what application designers would do with even more powerful hardware – and where current bottlenecks are hampering application performance.  Software system builders and microprocessor designers benefit from a closer interaction in determining what functionality should be performed in hardware vs software, particularly under the constraints provided by application designers. And application designers will benefit from better understanding current generation and emerging hardware designs in optimizing their code.
There will be a meeting on July 28, 2014 which is described below. This meeting will be a starting point for the new IDRE focus group. Many of the leading researchers will present current trends and success stories. We will discuss the issues faced by application developers and application designers particularly for domain-specific designs.

As part of this meeting, we are also looking for researchers  who are interested in leveraging many core to solve their “challenge” problems. Basically researchers should outline where their applications spend the most time, and what are the computationally challenging parts. Please contact us at hpc@ucla.edu if you are interested in participating.

Agenda:  

Agenda:

8:30 – 9:00 a.m.: Continental Breakfast  and Coffee
9:00 – 9:10 a.m.: Welcome  and Introduction to Area + Talks – Warren Mori
9:10 – 9:30 a.m.: Programming Languages – Jens Palsberg
9:30 – 9:50 a.m.: Compilers – Louis Noel Pouchet
9:50 – 10:10 a.m.: Customized Computing – From Single-Chip to Data-Centers – Jason Cong
10:10 – 10:30 a.m.: CMPs and Accelerators – Glenn Reinman
10:30 – 10:50 a.m.: Break
10:50 – 11:10 a.m.: Plasma Simulation using GPUs – Viktor Decyk
11:10 – 11:30 a.m.: Many-core Computing for Big Biomedical Data -Marc Suchard
11:30 – 11:50 a.m.: FPGA-based Acceleration of Medical Imaging Applications and Beyond – Peng Zhang
11:50 – 12:10 p.m.: Approximate Computing – Glenn Reinman
12:10 – 1:30 p.m.: Lunch Break and Panel Discussion
Panelists:  Marc Suchard, Viktor Decyk, Jens Palsberg, and Louis Noel Pouchet; Moderator – Glenn Reinman
1:30 – end.: Mixer