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High-performance programming: back to the hardware

May 3, 2018 @ 10:30 am - May 4, 2018 @ 4:00 pm


In collaboration with UCLA-ECE, IDRE  invites you to the workshop “High-Performance programming: back to hardware” with the following details:


  • Architecture of modern CPUs – brief overview
  • How to efficiently use CPU computing resources
  • Memory and cache architecture
  • How to use the memory system efficiently
  • Using multiple CPUs efficiently through concurrency
  • Memory model, locking, memory barriers

Fedor G Pikus, Ph.D.,
Chief Engineering Scientist,
Design to Silicon division,
Mentor Graphics Corp (Siemens business).

Timing: 10:30 AM – 4 PM on 5/3/2018 (Thursday), and 9:00 AM – 4:00 PM on 5/4/2018 (Friday)

Requirements: Please bring your own laptop for handson exercises.

RSVP – registration link (*lunch will be provided)

Abstract: The great “free lunch” of programming is over. Until recently, the programs just got faster by themselves as the time went by and the CPUs got upgraded. This does not happen anymore. The clock frequency of the new processors has peaked and even decreased slightly from the maximum. New architectures provide small improvements for existing programs, but only small improvements. The processors do get larger, more complex, and more powerful, but most of this new power goes into the increased number of processing cores and other “extra” computing units. To write efficient software, one now has to make good use of the available computing resources.

It used to be that to write any half-decent program, you had to know your hardware. Then, the hardware became hidden, abstracted behind higher-level languages; that was a good thing as the programmers could focus on writing programs in the way that expressed what they wanted to do, not how it had to be done. Now we find ourselves reaching for the old arcane knowledge of hardware again: from ones and zeros we came, to ones and zeros we return, from now and until the next level of abstractions and high-level languages are invented. Still, evolution is a spiral not a circle, and we do not need to discard what we learned about good programming practices simply because we need to write efficient programs again. To put it another way, just because our programs have to be as effective at getting every last bit of hardware performance as they were twenty years ago, does not mean they have to be as difficult to read and debug.

In pursuit of performance, we have at our disposal an amazing, powerful, and bewildering array of choices: concurrency (programming with multiple threads and multiple processes), atomic operations and lock-free programming, special CPU instructions and special accelerator hardware, memory and cache management, shared memory.

We will learn what really happens when your program is executed, what subtle details make a program slow or fast, and how to make the best use of the available computing resources. We will talk about which performance considerations should be considered early in the design stage, and which can be taken care of during implementation, or, even later, optimization, and what tools are available to measure the performance of your programs and their components. Most importantly, I want to show you how to learn more about writing efficient programs and discover new knowledge as you need it.

Bio: Fedor G Pikus is a Chief Engineering Scientist in the Design to Silicon division of Mentor Graphics Corp (Siemens business). His earlier positions included a Senior Software Engineer at Google and a Chief Software Architect for Calibre PERC, LVS, DFM at Mentor Graphics. He joined Mentor Graphics in 1998 when he made a switch from academic research in computational physics to software industry. His responsibilities as a Chief Scientist include planning long-term technical direction of Calibre products, directing and training the engineers who work on these products, design and architecture of the software, and research in new design and software technologies. Fedor has over 25 patents and over 100 papers and conference presentations on physics, EDA, software design, and C++ language.



May 3, 2018 @ 10:30 am
May 4, 2018 @ 4:00 pm
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IDRE Portal (5628 Math Sciences Building)
UCLA + Google Map


T V Singh
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